Substrate bonding with bonding material having rare earth metal

ABSTRACT

A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material.

PRIORITY

This patent application is a divisional patent application of U.S.patent application Ser. No. 12/434,886, filed May 4, 2009, entitled,“SUBSTRATE BONDING WITH BONDING MATERIAL HAVING RARE EARTH METAL,” andnaming John R. Martin, Timothy J. Frey, and Christine Tsau as inventors,the disclosure of which is incorporated herein, in its entirety, byreference.

U.S. patent application Ser. No. 12/434,886 claims priority fromprovisional U.S. Patent Application No. 61/095,754, filed Sep. 10, 2008,entitled, “SUBSTRATE BONDING WITH BONDING MATERIAL HAVING RARE EARTHMETALS,” and naming John R. Martin, Timothy J. Frey, and Christine Tsauas inventors, the disclosure of which is also incorporated herein, inits entirety, by reference.

RELATED APPLICATION

This patent application is related to U.S. Pat. No. 7,943,411, filed onMay 4, 2009, entitled, “APPARATUS AND METHOD OF WAFER BONDING USINGCOMPATIBLE ALLOY,” and naming John R. Martin, Timothy J. Frey, andChristine Tsau as inventors, the disclosure of which is incorporatedherein, in its entirety, by reference.

This patent application also is related to co-pending patent applicationSer. No. 13/161,108, filed on even date herewith, entitled, “METHOD OFSUBSTRATE BONDING WITH BONDING MATERIAL HAVING RARE EARTH METAL,” andnaming John R. Martin, Timothy J. Frey, and Christine Tsau as inventors,the disclosure of which is incorporated herein, in its entirety, byreference.

FIELD OF THE INVENTION

The invention generally relates to microchips and, more particularly,the invention relates to bonding substrates when forming microchips.

BACKGROUND OF THE INVENTION

A wide variety of microchips use caps to protect their interiorcomponents. For example, micro-electromechanical systems (“MEMSdevices”) often have a cap to protect their fragile microstructure. ManyMEMS devices typically have a glass seal to bond the silicon die caps tothe underlying MEMS chip. Such a seal, which can be hermetic, may havewidths on the order of about 150 to 400 microns. Undesirably, this sealfootprint increases die size, especially when there is little or nosupport circuitry on the die. As a consequence, fewer dies/microchipscan be formed from individual wafers, thus increasing per-unitfabrication costs.

Glass also can introduce contaminants and electrically isolate the capfrom the die. Although the latter problem can be accommodated bywirebonding to the cap, such a solution increases package height. Onealternative to using a glass seal involves use of a thermocompressionbonded metal. Undesirably, however, thermocompression bonding generallyrequires wafers to have minimal topography due to the high pressuresrequired in such processes.

SUMMARY OF THE INVENTION

In accordance with illustrative embodiments of the invention, amicrochip has a bonding material that bonds a first substrate to asecond substrate. The bonding material has, among other things, a rareearth metal and other material.

The first substrate may be either a chip or a wafer, and the secondsubstrate also may be either a chip or a wafer. Thus, the bondingmaterial facilitates a chip to chip bonding, a wafer to wafer bonding,or a chip to wafer bonding. Moreover, the bonding material may be asolder or a thermocompression material. The rare earth metal facilitatesbonding because, in various embodiments, the other material does notreadily bond with the first substrate in the absence of the rare earthmetal. The bonding material may have any useful concentration of rareearth metal, such as a concentration of between about 0.1 to 15.0percent (volume percent).

Therefore, various embodiments allow metals to be applied to one surfaceand bonded to a second surface with minimal restrictions as to thenature of the second surface. In this respect, it offers application andprocess versatility that, to the inventors' knowledge, only had beenavailable with glass seal/bond materials or nonhermetic polymericseal/bond materials.

The bonding material may form a hermetic seal, electrically connect thefirst substrate and the second substrate, or both. Deposition processes(e.g., sputtering processes) facilitate narrow and small-area bondstructures. For example, the bonding material may form a seal ringhaving a width of less than about 100 microns. In some embodiments, thefirst wafer has a least one pedestal with a top surface. The bondingmaterial thus is positioned between the second wafer and the top surfaceof the pedestal. Moreover, the bonding material may substantially coverthe interior surface of the first substrate, or cover no more than aportion of the same interior surface.

In accordance with another embodiment of the invention, a method ofbonding a first substrate and a second substrate forms at least onepedestal on the first substrate, and deposits bonding material having arare earth metal onto at least one of the pedestal and the secondsubstrate. The method then contacts the second substrate with the atleast one pedestal to form an intermediate apparatus. The bondingmaterial is positioned between the at least one pedestal and the secondsubstrate at this point. The method then heats the intermediateapparatus to cause the bonding material to bond with at least one of thefirst substrate and the second substrate.

To mitigate oxidation on the bonding material, the method may add acover material to the bonding material. This act may be performed beforecontacting the second substrate with the at least one pedestal. Inaddition, the at least one pedestal may be formed by a number ofprocesses, such as by etching the first substrate or simply securing amember onto a generally flat surface of the first substrate.

Some embodiments heat the intermediate apparatus to form athermocompression bond between the first substrate and the secondsubstrate. Alternatively, other embodiments may heat the intermediateapparatus to form a solder bond between the first substrate and thesecond substrate. Moreover, a bonding material may be disposed bysputtering, from a first source, the bonding material onto at least oneof the pedestal and the second substrate. The method further may sputtera cover material, from, for example, a second source, onto the bondingmaterial.

If the first and second substrates are wafers, the method may at leastpartially dice the first and second bonded wafers to produce a pluralityof individual chips. Some embodiments also form a via through at leastone of the first substrate and the second substrate. Among other things,the first substrate may have micro-electromechanical structure, and thesecond substrate may form a cap about the micro-electromechanicalstructure.

In accordance with another embodiment of the invention, a wafer bondingmethod deposits a metal alloy onto one or both of a MEMS wafer having atwo-dimensional array of MEMS devices or a second wafer. In preferredembodiments, the metal alloy has a rare earth metal. The method thenaligns the MEMS wafer and the second wafer to form an intermediateapparatus having the metal alloy between the wafers. Next, the methodheats the intermediate apparatus and brings the wafers into contact. Thestep of bringing the wafers into contact may occur before, after orsimultaneous with the start of heating. The contact pressure, time andtemperature of heating the intermediate apparatus is sufficient to allowthe rare earth metal to promote adhesion between at least a portion ofthe contacting surfaces. The intermediate apparatus is then cooled toform a plurality of substantially conductive hermetic sealing ringsabout the plurality of MEMS devices on the MEMS wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Those skilled in the art should more fully appreciate advantages ofvarious embodiments of the invention from the following “Description ofIllustrative Embodiments,” discussed with reference to the drawingssummarized immediately below.

FIG. 1 schematically shows a capped microchip that may be fabricated inaccordance with illustrative embodiments of the invention.

FIG. 2 shows a process of forming the capped microchip of FIG. 1 inaccordance with illustrative embodiments of the invention.

FIG. 3 schematically shows a cross-sectional view of two wafers to bebonded in accordance with illustrative embodiments of the invention.FIG. 3 also schematically shows a plan view of a portion of one of thosewafers.

FIG. 4 schematically shows a cross-sectional view of two wafers bondedin accordance with alternative embodiments of the invention.

FIG. 5 schematically shows a cross-sectional view of two wafers bondedin accordance with other embodiments of the invention.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Illustrative embodiments use a bonding material with a rare earthelement to bond wafers, chips, or wafers and chips. For example, thebonding material may be a solder and/or a thermocompression materialthat joins a wafer to another wafer. Details of illustrative embodimentsare discussed below.

FIG. 1 schematically shows a perspective view of a capped microchip 10fabricated in accordance with illustrative embodiments of the invention.To that end, the microchip 10 has a substrate 12 with functionalelements (e.g., circuitry, such as CMOS circuitry,microelectromechanical structure, or both) and a cap 14 circumscribingsome or all of the functional elements. For example, the microchip 10may implement the functionality of an accelerometer, such as that of anADXL202 IMEMS accelerometer or ADXL330 IMEMS accelerometer, both ofwhich have been distributed by Analog Devices, Inc. of Norwood, Mass. Asknown by those skilled in the art, the cap 14 protects the fragilemicrostructure within the MEMS device. It nevertheless should be notedthat discussion of a MEMS device or other specific microchip is forillustrative purposes only. Accordingly, details of various embodimentsapply to both MEMS and other devices. Additionally, discussion ofbonding two wafers, two microchips or a wafer, and a microchip is forillustrative purposes only and does not preclude bonding between otherstructures or more than two structures.

In accordance with illustrative embodiments of the invention, themicrochip 10 has a specially configured seal ring bonding the cap 14 tothe substrate 12. Specifically, the seal ring is formed from a bondingmaterial/alloy 24 having, in combination, at least one rare earth metaland a metal/element/alloy. The rare earth metal in the alloy/elementenables bonding to wafers/chips that the bonding material 24, undersimilar bonding conditions, may not bond to absent the rare earth metal.Accordingly, the bonding material 24 readily bonds to both the substrate12 and the cap 14 to provide a hermetic seal (if required by theapplication).

As used herein, the term “rare earth” metal or element includes thelanthanide series, as well as scandium and yttrium. For example, incertain applications, lanthanum and yttrium should provide satisfactoryresults.

Moreover, the seal ring also electrically connects the cap 14 with thesubstrate 12, thus allowing the potential between the cap 14 and thesubstrate 12 to be controlled. Accordingly, due to the high chemicalreactivity of the rare earth metal within the alloy, the surfaces of thecap 14 and the substrate 12 do not require extensive surface scrubbingor additional preparation steps.

Use of the rare earth metal enables a wide range of potential materialsfor use as the bonding material 24. For example, metals having lowtoxicity and low contamination may be more preferable to bond the cap 14to the substrate 12. As discussed in greater detail below, the seal ringmay be formed through a number of processes, such as a solderingprocess, an alloy-forming process, or a thermocompression process.Unlike many solders, however, the seal ring may have a very small width,such as on the order of about 100 microns. As such, the seal ring shouldoccupy less chip real estate than many prior art seal rings, favorablyreducing the overall chip size.

FIG. 2 shows a general process of forming the microchip 10 of FIG. 1 inaccordance with illustrative embodiments of the invention. It should benoted that this method is a simplified summary of the overall process offorming the microchip 10 and thus, does not include a number of othersteps that may be included, such as chip testing and preparation ofcertain equipment. Moreover, some steps may be performed in a differentorder, or, in some instances, omitted.

In general, the process of FIG. 2 forms a plurality of microchips (e.g.,the microchip 10 of FIG. 1) in parallel by simultaneously fabricating atwo dimensional array of individual devices (e.g., MEMS devices) on adevice wafer 16 (shown in FIGS. 3-5, discussed below), and sealing eachof those devices with caps 14 formed from a single cap wafer 18 (alsoshown in FIGS. 3-5, discussed below). Some embodiments, however, processa single device at a time and thus, do not employ these noted batchprocesses.

The process of FIG. 2 begins at step 200, which forms pedestals 20 onthe surface of the substrate 12. Specifically, FIG. 3 schematicallyshows a device wafer 16 having a two dimensional array of MEMS devices,and a cap wafer 18 for protecting the MEMS devices on the device wafer16. The cap wafer 18 in this embodiment has a generally flat topography,while the device wafer 16 has a relatively complex topography. Forexample, if implementing MEMS accelerometers, the device wafer 16generally may have a topology similar to that disclosed by U.S. Pat. No.5,939,633, owned by Analog Devices, Inc. and incorporated herein, in itsentirety, by reference.

Accordingly, conventional micromachining processes form each of theplurality of devices on the device wafer 16 to have, among other things,a plurality of springs (not shown) movably supporting a mass 22 abovethe substrate 12. FIG. 3 schematically shows the mass 22 supported abovethe substrate 12 in this manner. The process also may form vias (notshown) and/or bond pads (not shown) to electrically connect with themass 22 and/or circuitry of each device.

As noted above, illustrative embodiments form a plurality of pedestals20 that each generally circumscribe the movable mass 22 of one device.In other words, each device has at least one pedestal 20 around its mass22. Optionally, the pedestal 20 of a device may enclose more than onemass 22, and a device may have more than one pedestal 20. To reduceprocess steps and improve efficiency, the method preferably forms thesepedestals 20 as it forms the movable mass 22, springs, and othermicrostructure on the device wafer 16.

By way of example, the pedestals 20 may be formed by etching materialfrom the device wafer 16. Accordingly, if the device wafer 16 is formedfrom single crystal silicon, then the pedestals 20 also are formed fromsingle crystal silicon (i.e., because they are integral with and formedfrom the device wafer 16). Alternatively, the method may form thepedestals 20 by disposing a material onto the device wafer 16. Forexample, the method may deposit polysilicon onto the device wafer 16 toform the pedestals 20. Optionally, a dielectric material can be used toform pedestal 20, or as a layer under some or all of pedestal 20, toelectrically isolate selected regions of substrate 12 from cap 14. Inyet another embodiment, the method may secure separate, pre-madecircumscribing components onto the device wafer 16.

If the cap wafer 18 is very close to the device wafer 16, then the twowafers effectively may form a capillary that wicks the bonding material24 across the microstructure (if the bonding material 24 is in a liquidstate). The height of the pedestals 20 thus should be controlled toavoid this undesirable consequence if the bonding material is in aliquid state. One advantage of processing at a temperature below themelting point is that such capillary wicking effects are avoided. If thebonding process is close to, but below, the melting point, the bondingmaterial is soft. Therefore, moderate force is sufficient to deform thebonding material 24 to accommodate normal variations in wafertopography. In this discussion, the term “melting point” refers to thetemperature at which the solid becomes a liquid, and such term isintended to broadly cover solid-liquid phase transitions, such as thosethat occur in mixtures at a eutectic point.

To reduce the chip real estate required for the seal ring being formed,illustrative embodiments form the pedestals 20 to have a very smallwidth. For example, the pedestals 20 may have a width of about 100microns or less. Of course, some embodiments may form the pedestals 20to have greater widths and thus, pedestal widths greater than 100microns may still be within the scope of various embodiments of theinvention.

After forming the pedestals 20, the method adds bonding material 24,which includes a rare earth metal, to one of the wafers (step 202). Themethod may add the bonding material 24 in any number of ways. FIG. 3shows a method of adding the bonding material 24 to the entire bottomsurface of the cap wafer 18. This material may be added using any numberof a variety of conventional techniques, such as sputtering, blanketcoating, other processes.

In one embodiment, the method sputters a 0.5 to 4.0 micron thick alloyof tin and rare earth metal onto the bottom of the cap wafer 18 (e.g.,see FIG. 3). For example, the method first blanket sputters tin or a tinalloy onto the cap wafer 18, and then, without breaking vacuum, sputtersa rare earth metal onto the tin layer. Alternatively, rather thansequentially applying the alloy materials, the method sputters a mixturealloy including the rare earth metal onto the appropriate surface.

Next, the method may sputter a thinner layer (e.g., 0.05 to one micronthick) of material that does not contain rare earth metal, onto thefirst layer. This second layer primarily acts as an oxygen barrier toprevent/mitigate oxidation of the rare earth alloy. As such, this layercan be referred to as a “cover layer.” The cover layer may be thematerial used in the first layer (tin or tin alloy in the embodimentdescribed above), or a different material, such as gold.

It should be noted that discussion of a sputtering process is forsimplicity only and thus, not intended to limit other embodiments of theinvention. For example, some embodiments may apply the bonding material24 using a transfer process. Accordingly, those skilled in the art mayuse other techniques for applying the bonding material 24 to theappropriate wafer 16 or 18.

Alternatively, the method may add the bonding material 24 to both wafers16 and 18, or to the top facing surface of the pedestal rings 20 on thedevice wafer 16.

Any number of different alloys may be used, depending upon theapplication. Toxicity, contamination, and other factors should be takeninto consideration. For example, many applications require a lead-freealloy. In addition to lead, toxicity also discourages use of othermaterials, such as cadmium and mercury. Alloys and the cover materialalso may be selected based upon their eutectic temperature. For example,higher eutectic temperature materials/alloys (e.g., above 300 degreesC.) should be considered based on the requirements of subsequent thermalexposures. For example, if the die will subsequently be packaged inplastic using standard transfer molding techniques, the alloy should becapable of withstanding the 175 degree C. transfer molding processtemperature.

As another example, CMOS devices should avoid deep level trap metals,such as gold. Specifically, various embodiments select from metalscustomarily used in a CMOS wafer fabrication plant. Among others, thosemetals include aluminum, germanium, tungsten, and titanium. Such typesof metals are considered to be “CMOS compatible” metals. In oneillustrative embodiment of forming bond material 24, 0.5 to 4 microns ofaluminum or an aluminum alloy suitable for use in a CMOS waferfabrication facility may be deposited on an optional barrier/bondinglayer, such as titanium-tungsten. A rare earth metal layer, 0.1 to 1.0microns thick, is then deposited on this aluminum or aluminum alloy,followed by a thin cover layer that may conveniently be the samealuminum or aluminum alloy. The aluminum alloys used for interconnectlayers of integrated circuit wafers are one class of alloys that may beuseful in this embodiment. Alloys of aluminum and germanium are alsoattractive for this embodiment because they have a relatively lowmelting temperature (424 degrees C. for the eutectic composition).Metals are soft and readily deformed near their melting temperature, souse of a low melting temperature alloy allows bond surfaces to bepressed into atomic scale contact at relatively low pressure andtemperature. This is particularly advantageous for delicate or thermallysensitive materials, or those with a high bond area such that achievingatomic scale contact requires that the applied bond force approach orexceed the limits of available equipment.

Further material constraints may arise in other applications. Forexample, in stiction sensitive applications, alloy selection may belimited to metals having negligible vapor pressure at anticipatedbonding temperatures. In addition, the exposed metal (i.e., the sourceof vapor) may be minimized by removing it from the cap wafer cavitysurface. Metals such as indium and bismuth therefore may cause stictionif they are volatilized and inadvertently deposited onto closely spacedmicrostructures during the wafer bonding process. Moreover, tinundesirably can spontaneously generate whiskers. In fact, addition of arare earth metal to tin appears to enhance this characteristic.Post-treating the seals and interconnects with an atomic layerdeposition film may reduce this phenomenon.

One of ordinary skill in the art thus should select the appropriate basealloy or element to mix with a rare earth metal based upon the intendedapplication. The base alloy may include binary alloys, such as thosebased on tin/silver, gold/tin, gold/silicon/and germanium/aluminum. Forexample, 96.5 tin-3.5 silver has an eutectic temperature at about 221degrees C., 55 germanium-45 aluminum has an eutectic temperature atabout 424 degrees C. Addition of a small amount of rare earth metalshould not appreciably change the eutectic process temperatures. Alloyshaving more than two elements also may receive a rare earth metal forthe noted purposes. Other embodiments may use single element basematerials, such as aluminum.

Illustrative embodiments add a relatively small percentage of rare earthmetal to the base alloy. The method selects the appropriate percentageprimarily based upon the bonding strength desired for the ultimatealloy. For example, the rare earth alloy may have a concentration ofbetween about 0.1 and about 15.0 percent rare earth metal. Morespecifically, the rare earth alloy may have a concentration of betweenabout 0.5 and about 10.0 percent rare earth metal.

After adding the bonding material 24, the process continues to step 204,which couples together the substrate and cap wafers 16 and 18 to form an“intermediate apparatus.” To that end, conventional processes adhere thebonding material 24 to one or both of the wafers, and bring the waferstogether. Due to the nature of the structure and bonding material 24,however, illustrative embodiments do not necessarily require precisealignment to bring the wafers together. In fact, the surfaces often donot require special surface preparation—instead, the surfaces are readyfor bonding. Alternative embodiments, however, may prepare the surfaces,such as by removing any surface oxides that could reduce bondingefficiency.

The bonding material 24 may be a solder, a thermocompression material orother material sufficient to accomplish the desired goals. If it is asolder, then conventional processes heat the bonding material 24 to atemperature and pressure sufficient to ensure intimate contact at thebond surfaces of the wafers. The temperature and time of contact shouldbe sufficient to allow the rare earth metal to diffuse to the interfaceand promote adhesion between the wafer surfaces. Similarly, if using acover layer on tin alloy/rare earth layers or aluminum alloy/rare earthlayers, then this step allows the materials to interdiffuse such thatthe rare earth metal promotes adhesion between the wafer surfaces. Thebonding material 24 of this embodiment thus connects between the topsurface of each pedestal 20 and the face of the cap wafer 18.

Each pedestal 20 and accompanying bonding material 24 thus is consideredto form a seal ring around its respective microstructure. It should benoted that use of the term “ring” should not be construed to suggestthat the seal ring takes on any particular shape. Instead, each sealring may be any reasonably appropriate shape as required by theapplication and chip design process. For example, FIG. 3 shows agenerally rectangular seal ring. Optionally, the pedestal 20 of adevice/microchip 10 may enclose more than one mass 22, and/or adevice/microchip 10 may have more than one pedestal 20.

If it is a thermocompression material, then the process does not heatthe bonding material 24 to its liquid phase. Instead, the process usesthermocompressive bonding techniques by applying forces at prespecifiedtemperatures and times to achieve atomic scale contact of the bondsurfaces, and allow the rare earth metal to diffuse to the interface topromote bonding between those surfaces. Of course, selection of anappropriate bonding material 24 (e.g., a rare earth metal with aluminumor an aluminum alloy) enables the method to reduce the thermocompressiontemperature.

Some embodiments do not use an entirely different cover layer material,such as gold, to prevent oxidation of the rare earth alloy layer. Forexample, a rare earth alloy with aluminum may simply use an aluminumcover layer to prevent oxidation. Specifically, as known by thoseskilled in the art, aluminum oxide is generally brittle and thus, shoulddiffuse into the aluminum when subjected to high temperatures andpressures of a thermocompression process. Alternatively, the inventorsbelieve that some rare earth alloys, such as the noted aluminum alloy,may not require a cover layer. Specifically, the inventors believe thataluminum oxide formed on the exposed face of the rare earth/aluminumalloy may substantially mitigate formation of oxides normally associatedwith rare earth metals.

The method concludes at step 206, which separates the dies from theirrespective wafers 16 and 18. Specifically, after permitting the coupledwafers 16 and 18 to cool a sufficient period of time, conventionaldicing processes may cut the bonded wafers to produce a plurality ofindependent microchips 10. Among others, conventional saw or laserdicing processes may separate the dies 10.

Some embodiments may cut only one wafer, and cut the other wafer at asubsequent processing step. For example, the method may cut the capwafer 18 only, thus exposing a portion of the device wafer 16 (e.g.,exposing bond pads). Subsequent testing processes may use these bondpads to test the microchips 10 before dicing the device wafer 16.

Illustrative embodiments may use any of a number of techniques foraligning the cutting mechanism with the two bonded wafers. For example,some embodiments may use infrared sensors or other optical applicationsfrom the sides of the device wafer 16. Other embodiments may remove someof the bonding material 24 before bonding, or selectively deposit thebonding material 24 onto the cap wafer 18 to facilitate alignment visionsystems. FIG. 4 schematically shows one such embodiment.

FIG. 5 schematically shows another embodiment with an opposite pedestalarrangement; namely, the pedestals 20 are formed on/from the cap wafer18. To that end, this method may pattern and etch the cap wafer 18, andthen deposit the bonding material 24 discussed above. Similarapplication techniques may be used. For example, conventional sputteringtechniques may apply the bonding material 24 as a blanket coat, andoptionally remove portions of it as shown in FIG. 4. Alternatively, inthis and other embodiments, the bonding material 24 may be stamped usinga transfer printing process or formed using a method such as inkjetprinting. For example, this process may use a solder film (hot wafer ormolten solder). As an alternative step, the transfer equipment may scrubthe wafer to ensure that surface oxide does not affect contact quality.Other embodiments may thin-film pattern and etch the bonding material24.

Some embodiments use the bonding material 24 without the pedestals 20.Instead, in those cases, the bonding material 24 alone may act as theseal ring. In yet other embodiments, both wafers 16 and 18 havepedestals 20.

Accordingly, various embodiments of the invention provide a solution toa long felt need in the art. Specifically, among other things, thebonding material 24 provides a conductive bond that readily couples witha wide variety of material surfaces. The resulting bond, which may beformed between two wafers, two chips, or a chip and a wafer—with orsometimes without alignment—should take up less chip real estate. Forexample, a tin/rare earth, aluminum/rare earth, oraluminum-germanium/rare earth bonding material should provide ahermetic, conductive bond with a much smaller width than that of aconventional glass frit bond. Consequently, the bonding material 24 aidsin reducing chip size, causing wafer fabrication yield to increase, thusdriving down per-part costs. In addition, illustrative embodimentspermit bonding by metalizing one of two surfaces only (e.g., only onewafer surface is metalized in a wafer-to-wafer bond).

Although the above discussion discloses various exemplary embodiments ofthe invention, it should be apparent that those skilled in the art canmake various modifications that will achieve some of the advantages ofthe invention without departing from the true scope of the invention. Inaddition, characteristics of the described embodiments may be combinedto yield similar results.

1. A microchip comprising: a first semiconductor substrate having atleast one pedestal ring with a top surface; a second semiconductorsubstrate; and a bonding material bonding the first and secondsubstrates, the bonding material comprising an alloy comprising a rareearth metal and other conductive metal, the bonding material beingbetween the second substrate and the top surface of the pedestal ring,the bonding material, pedestal ring, first substrate and secondsubstrate forming a chamber containing MEMS structure.
 2. The microchipas defined by claim 1 wherein the first substrate comprises a chip or awafer and the second substrate comprises a chip or a wafer.
 3. Themicrochip as defined by claim 1 wherein the first substrate comprises awafer having a plurality of MEMS devices, the second substratecomprising a wafer having a plurality of caps, the bonding materialforming a plurality of sealing rings hermetically sealing the MEMSdevices.
 4. The microchip as defined by claim 1 wherein the firstsubstrate has an interior surface, the bonding material substantiallycovering the interior surface.
 5. The microchip as defined by claim 1wherein the other material does not readily bond with the firstsubstrate in the absence of the rare earth metal.
 6. The microchip asdefined by claim 1 wherein the bonding material electrically connectsthe first substrate and the second substrate.
 7. The microchip asdefined by claim 1 wherein the bonding material forms a seal ring havinga width of less than about 100 microns.
 8. The microchip as defined byclaim 1 wherein the at least one pedestal ring is formed at least inpart from a semiconductor material and is integral with the firstsemiconductor substrate.
 9. A microchip comprising: a first substrate; asecond substrate; and a bonding material bonding the first and secondsubstrates, the bonding material comprising a rare earth metal and othermaterial, wherein the other material does not readily bond with thefirst substrate in the absence of the rare earth metal.
 10. Themicrochip as defined by claim 9 wherein the first substrate comprises achip or a wafer and the second substrate comprises a chip or a wafer.11. The microchip as defined by claim 9 wherein the first substratecomprises a wafer having a plurality of MEMS devices, the secondsubstrate comprising a wafer having a plurality of caps, the bondingmaterial forming a plurality of sealing rings hermetically sealing theMEMS devices.
 12. The microchip as defined by claim 9 wherein the firstsubstrate has an interior surface, the bonding material substantiallycovering the interior surface.
 13. The microchip as defined by claim 9wherein the bonding material electrically connects the first substrateand the second substrate.
 14. The microchip as defined by claim 9wherein the bonding material forms a seal ring having a width of lessthan about 100 microns.
 15. The microchip as defined by claim 9 whereinthe first substrate has at least one pedestal ring with a top surface,the bonding material being between the second substrate and the topsurface of the pedestal ring.
 16. A microchip comprising: a firstsubstrate; a second substrate; and a bonding material bonding the firstand second substrates, the bonding material comprising a rare earthmetal and other material, the bonding material forming a seal ringhaving a width of less than about 100 microns.
 17. The microchip asdefined by claim 16 wherein the first substrate comprises a chip or awafer and the second substrate comprises a chip or a wafer.
 18. Themicrochip as defined by claim 16 wherein the first substrate comprises awafer having a plurality of MEMS devices, the second substratecomprising a wafer having a plurality of caps, the bonding materialforming a plurality of sealing rings hermetically sealing the MEMSdevices.
 19. The microchip as defined by claim 16 wherein the firstsubstrate has an interior surface, the bonding material substantiallycovering the interior surface.
 20. The microchip as defined by claim 16wherein the other material does not readily bond with the firstsubstrate in the absence of the rare earth metal.
 21. The microchip asdefined by claim 16 wherein the bonding material electrically connectsthe first substrate and the second substrate.
 22. The microchip asdefined by claim 16 wherein the first substrate has at least onepedestal ring with a top surface, the bonding material being between thesecond substrate and the top surface of the pedestal ring.